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Issue No.02 - Mar.-Apr. (2014 vol.16)
pp: 16-20
Amit Kumar Singh Tomar , Lakshmi Narain College of Technology, India
Rita Jain , Lakshmi Narain College of Technology, India
ABSTRACT
These days, most microprocessor and microcontroller designs are based on a Reduced Instruction Set Computer (RISC) core, and many operations--such as discrete cosine transform (DCT), inverse DCT, discrete Fourier transform (DFT), and fast Fourier transform (FFT)--are performed by a digital signal processor (DSP) system. Here, the authors present the design of a RISC and DSP system that uses very high-density logic (VHDL) and a field-programmable gate array (FPGA). This RISC is a 20-bit processor.
INDEX TERMS
Reduced instruction set computing, Field programmable gate arrays, Registers, Discrete cosine transforms, Discrete Fourier transforms, Digital signal processing, Logic gates,scientific computing, arithmetic logic unit, ALU, CPU, control unit, CU, field-programmable gate array, FPGA, general-purpose register, GPR, instruction register, IR, program counter, PC, reduced instruction set computer, RISC, register set, RS, multiply and accumulates, MACs, very large instruction word, VLIW
CITATION
Amit Kumar Singh Tomar, Rita Jain, "20-Bit RISC and DSP System Design in an FPGA", Computing in Science & Engineering, vol.16, no. 2, pp. 16-20, Mar.-Apr. 2014, doi:10.1109/MCSE.2013.20
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