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Issue No.06 - November/December (2010 vol.12)
pp: 80-87
ABSTRACT
<p>Unlike other socket-based reconfigurable coprocessors, the Convey HC-1 contains nearly 40 field-programmable gate arrays, scatter-gather memory modules, a high-capacity crossbar switch, and a fully coherent memory system.</p>
INDEX TERMS
Reconfigurable computing, heterogeneous computing, hybrid computing, high-performance computing, field-programmable gate arrays
CITATION
Jason D. Bakos, "High-Performance Heterogeneous Computing with the Convey HC-1", Computing in Science & Engineering, vol.12, no. 6, pp. 80-87, November/December 2010, doi:10.1109/MCSE.2010.135
REFERENCES
1. J. Leidel, "Design Philosophies for Memory-Centric Instruction Set Architectures," presentation, Symp. Application Accelerators in High Performance Computing (SAAHPC'10), 2010; http://saahpc.ncsa.illinois.edu/presentations/ day1/session4presentation_Leidel.pdf .
2. Convey Computer, "Convey Computer Announces Record-Breaking Smith-Waterman Acceleration of 172x," press release, 24 May 2010; www.conveycomputer.com/ResourcesConvey_Announces_Record_Breaking_Smith_Waterman_Acceleration.pdf .
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