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Nallatech In-Socket FPGA Front-Side Bus Accelerator
March/April 2010 (vol. 12 no. 2)
pp. 78-83

Field-programmable gate arrays, which are more flexible than application-specific integrated circuits, have emerged as a low-power alternative to CPUs.

1. T. El-Ghazawi et al., "The Promise of High-Performance Reconfigurable Computing," Computer, vol. 41, no. 2, 2008, pp. 78–85.
2. L. Ling et al., "High-Performance, Energy-Efficient Platforms Using In-Socket FPGA Accelerators," Proc. Int'l Symp. Field-Programmable Gate Arrays, ACM Press, 2009, pp. 261–264.
3. FSB Family–Product Brief, Nallatech, 2009; english7630.pdf.
4. Virtex-5 FPGA RocketIO GTP Transceiver User Guide, Xilinx, 2009; .
5. G. Genest, R. Chamberlain, and R. Bruce, "Programming an FPGA-Based Super Computer Using a C-to-VHDL Compiler: Dime-C," Proc. 2nd NASA/ESA Conf. Adaptive Hardware and Systems, IEEE Press, 2007, pp. 280–286.
6. C. Li, C. Ding, and K. Shen, "Quantifying the Cost of Context Switch," Proc. Workshop Experimental Computer Science, ACM Press, 2007, article 2.

Index Terms:
Field-programmable gate arrays, Xeon, accelerators, reconfigurable, compiler, bandwidth, Xilinx
Craig Steffen, Gildas Genest, "Nallatech In-Socket FPGA Front-Side Bus Accelerator," Computing in Science and Engineering, vol. 12, no. 2, pp. 78-83, March-April 2010, doi:10.1109/MCSE.2010.45
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