Issue No.10 - October (vol.46 vol.46)
Published by the IEEE Computer Society
Srinivas Devadas , MIT
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MC.2013.373
With exascale multicores, the question of how to efficiently support a shared memory model is of paramount importance. As programmers demand the convenience of coherent shared memory, ever-growing core counts place higher demands on memory subsystems, and increasing on-chip distances mean that interconnect delays exert a significant effect on memory access latencies.
Special issues and sections, Multicore processing, Memory management, System-on-chip, Memory management,soft errors, multicore architecture, cache coherence, directory protocol, on-chip network
Srinivas Devadas, "Toward a Coherent Multicore Memory Model", Computer, vol.46, Issue No.10 - October, October 2013, pp. 30-31, doi:10.1109/MC.2013.373