The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.11 - November (2011 vol.44)
pp: 22-30
John Shalf , Lawrence Berkeley National Laboratory
Dan Quinlan , Lawrence Livermore National Laboratory
Curtis Janssen , Sandia National Laboratories
ABSTRACT
The rapid and disruptive changes anticipated in hardware design over this next decade necessitate a more agile development process, such as the hardware-software co-design processes developed for rapid product development in the embedded space. This article will describe the structure of the co-design process as applied to supercomputing systems, introduce the role of architectural simulation and code analysis to enable co-design, and describe the CoDEx project that is developing tools to accelerate the iterative co-design cycle for the DOE exascale computing program.
INDEX TERMS
High-performance computing, Exascale systems, Hardware-software codesign
CITATION
John Shalf, Dan Quinlan, Curtis Janssen, "Rethinking Hardware-Software Codesign for Exascale Systems", Computer, vol.44, no. 11, pp. 22-30, November 2011, doi:10.1109/MC.2011.300
REFERENCES
1. P. Kogge et al., "Exascale Computing Study: Technology Challenges in Achieving Exascale Systems," IPTO tech. report TR-2008-13, 2008, DARPA; rwww.cse.nd.edu/Reports/2008/TR-2008-13.pdf.
2. K. Asanovic et al., "The Landscape of Parallel Computing Research: A View from Berkeley," tech. report UCB/EECS-2006-183, 2006, EECS Dept., UC Berkeley; www.eecs.berkeley.edu/Pubs/TechRpts/2006 EECS-2006-183.pdf.
3. C.L. Janssen et al., "A Simulator for Large-Scale Parallel Architectures," Int'l J. Parallel and Distributed Systems, vol. 1, no. 2, 2010, pp. 57-73.
4. S.D. Hammond et al., "WARPP: A Toolkit for Simulating High-Performance Parallel Scientific Codes," Proc. 2nd Int'l Conf. Simulation Tools and Techniques (Simutools 09), Inst. for Computer Sciences, Social-Informatics, and Telecommunications Eng., 2009, pp. 1-19.
5. V.S. Adve et al., "Compiler-Optimized Simulation of Large-Scale Applications on High-Performance Architectures," J. Parallel and Distributed Computing, vol. 62, no. 3, 2002, pp. 393-426.
6. R. Susukita et al., "Performance Prediction of Large-Scale Parallel Systems and Applications Using Macro-Level Simulation," Proc. Int'l Conf. High-Performance Computing, Networking, Storage, and Analysis (SC 08), ACM, 2008, pp. 1-9.
7. A. Krasnov et al., "RAMP BLUE: A Message-Passing Manycore System in FPGAs," Proc. Int'l Conf. Field Programmable Logic and Applications (FPL 07), 2007; http://ramp.eecs.berkeley.edu/Publications RAMP%20Blue%20FPL%202007.pdf.
8. M. Mohiyuddin et al., "A Design Methodology for Domain-Optimized Power-Efficient Supercomputing," Proc. Int'l Conf. High-Performance Computing, Networking, Storage, and Analysis (SC 09), ACM, 2009, pp. 1-12.
9. D. Donofrio et al., "Energy-Efficient Computing for Extreme-Scale Science," Computer, Nov. 2009, pp. 62-71, 2009.
10. J. Krueger et al., "Hardware-Software Codesign for Energy-Efficient Seismic Modeling," Proc. Int'l Conf. High-Performance Computing, Networking, Storage, and Analysis (SC 11), ACM, to be published, 2011.
23 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool