|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
| | ||
| Search | ||
| ||
| ASCII Text | x | ||
| André DeHon, Benjamin Gojman, "Crystals and Snowflakes: Building Computation from Nanowire Crossbars," Computer, vol. 44, no. 2, pp. 37-45, February, 2011. | |||
| BibTex | x | ||
| @article{ 10.1109/MC.2011.44, author = {André DeHon and Benjamin Gojman}, title = {Crystals and Snowflakes: Building Computation from Nanowire Crossbars}, journal ={Computer}, volume = {44}, number = {2}, issn = {0018-9162}, year = {2011}, pages = {37-45}, doi = {http://doi.ieeecomputersociety.org/10.1109/MC.2011.44}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - Computer TI - Crystals and Snowflakes: Building Computation from Nanowire Crossbars IS - 2 SN - 0018-9162 SP37 EP45 EPD - 37-45 A1 - André DeHon, A1 - Benjamin Gojman, PY - 2011 KW - Lithography KW - Self-assembly KW - Bottom-up synthesis KW - Programmable logic arrays (PLAs) KW - Nanowires KW - Reconfigurable computing VL - 44 JA - Computer ER - | |||
1. Y. Cui et al., "Diameter-Controlled Synthesis of Single Crystal Silicon Nanowires," Applied Physics Letters, vol. 78, no. 15, 2001, pp. 2214-2216.
2. D. Whang et al., "Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems," Nanoletters, Sept. 2003, pp. 1255-1259.
3. C. Yang, Z. Zhong, and C.M. Lieber, "Encoding Electronic Properties by Synthesis of Axial Modulation-Doped Silicon Nanowires," Science,25 Nov. 2005, pp. 1304-1307.
4. A. De Hon, "Nanowire-Based Programmable Architectures," ACM J. Emerging Technologies in Computing Systems, vol. 1, no. 2, 2005, pp. 109-162.
5. B. Gojman et al., "Inversion Schemes for Sublithographic Programmable Logic Arrays," IET Computers and Digital Techniques, Nov. 2009, pp. 625-642.
6. W.B. Culbertson et al., "Defect Tolerance on the TERAMAC Custom Computer," Proc. IEEE Symp. FPGAs for Custom Computing Machines (FCCM 97), IEEE Press, 1997, pp. 116-123.
7. A. De Hon and H. Naeimi, "Seven Strategies for Tolerating Highly Defective Fabrication," IEEE Design and Test of Computers, July/Aug. 2005, pp. 306-315.
8. B. Gojman and A. De Hon, "VMATCH: Using Logical Variation to Counteract Physical Variation in Bottom-Up, Nanoscale Systems," Proc. Int'l Conf. Field-Programmable Technology (FPT 09), IEEE Press, 2009, pp. 78-87.
9. B. Gojman et al., "3D Nanowire-Based Programmable Logic," Proc. Int'l Conf. Nano-Networks (NanoNet 06), IEEE Press, 2006, pp. 1-5.
10. Y. Luo et al., "Two-Dimensional Molecular Electronics Circuits," ChemPhysChem, vol. 3, no. 6, 2002, pp. 519-525.
11. S.C. Goldstein and M. Budiu, "NanoFabrics: Spatial Computing Using Molecular Electronics," Proc. Int'l Symp. Computer Architectures (ISCA 01), IEEE CS Press, 2001, pp. 178-189.
12. D.B. Strukov and K.K. Likharev, "CMOL FPGA: A Reconfigurable Architecture for Hybrid Digital Circuits with Two-Terminal Nanodevices," Nanotechnology, June 2005, pp. 888-900.
13. G.S. Snider and R.S. Williams, "Nano/CMOS Architectures Using a Field-Programmable Nanowire Interconnect," Nanotechnology, Jan. 2007; http://iopscience.iop.org/0957-4484/18/3 035204.
14. J.E. Green et al., "A 160-Kilobit Molecular Electronic Memory Patterned at 1011 Bits Per Square Centimetre," Nature,25 Jan. 2007, pp. 414-417.

