The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.03 - March (2010 vol.43)
pp: 24-32
Angela C. Sodan , University of Windsor
Jacob Machina , University of Windsor
Arash Deshmeh , University of Windsor
Kevin Macnaughton , University of Windsor
Bryan Esbaugh , University of Windsor
ABSTRACT
Multicore and multithreaded CPUs have become the new approach to obtaining increases in CPU performance. Numeric applications mostly benefit from a large number of computationally powerful cores. Servers typically benefit more if chip circuitry is used for maximizing throughput via multiple threads per core.
INDEX TERMS
Multicore processors, Multithreaded cores, GPUs, Heterogeneous cores, Application-level parallelism, Chip interconnects, Power efficiency
CITATION
Angela C. Sodan, Jacob Machina, Arash Deshmeh, Kevin Macnaughton, Bryan Esbaugh, "Parallelism via Multithreaded and Multicore CPUs", Computer, vol.43, no. 3, pp. 24-32, March 2010, doi:10.1109/MC.2010.75
REFERENCES
1. S. Borkar, "Thousand Core Chips—A Technology Perspective," Proc. 44th Design Automation Conference (DAC 07), ACM Press, 2007, pp. 746-749.
2. T. Duff, "A Conversation with Kurt Akeley and Pat Hanrathan," ACM Queue, Mar./Apr. 2008, pp. 11-17.
3. D. Marr et al., "Hyper-Threading Technology Architecture and Microarchitecture," Intel Technology J., vol. 6, no. 1, 2002, pp. 4-15.
4. J. Burns and J.L. Gaudiot, "SMT Layout Overhead and Scalability," IEEE Trans. Parallel and Distributed Systems, Feb. 2002, pp.142-155.
5. T. Ungerer, B. Robic, and J. Šilc, "A Survey of Processors with Explicit Multithreading," ACM Computing Surveys, Mar. 2003, pp. 29-63.
6. R. Kumar, V. Zyuban, and D.M. Tullsen, "Interconnections in Multicore Architectures: Understanding Mechanisms, Overheads, and Scaling," Proc. 32nd Ann. Int'l Symp. Computer Architecture (ISCA 05), ACM Press, 2005, pp. 408-419.
7. M. Mantor, "Entering the Golden Age of Heterogeneous Computing" ; http://ati.amd.com/technology/streamcomputing IUCAA_Pune_PEEP_2008.pdf.
8. D. Kanter, "NVIDIA's GT200: Inside a Parallel Processor" ; www.realworldtech.compage.cfm?ArticleID=RWT090808195242 .
9. H.Q. Le et al., "IBM POWER6 Microarchitecture," IBM J. Research and Development, vol. 51, no. 6, 2007, pp. 639-662.
10. IBM Blue Gene Team, "Overview of the IBM Blue Gene/P Project," IBM J. Research and Development, Jan.-Mar. 2008, pp. 199-220.
11. K.J. Nesbit, J. Laudon, and J.E. Smith, "Virtual Private Caches," Proc. Int'l Symp. Computer Architecture (ISCA 07), IEEE CS Press, 2007, pp. 57-68.
12. N. Aggarwal et al., "Isolation in Commodity Multicore Processors," Computer, June 2007, pp. 49-59.
13. M.D. Hill and M.R. Marty, "Amdahl's Law in the Multicore Era," Computer, July 2008, pp. 33-38.
14. D. Dice et al., "Early Experiences with a Commercial Hardware Transactional Memory Implementation," Proc. 14th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 09), ACM Press, 2009, pp. 157-168.
15. R. Kumar et al., "Heterogeneous Chip Multiprocessors," Computer, Nov. 2005, pp. 32-38.
16. L.A. Barroso and U. Hoelzle, "The Case for Energy-Proportional Computing," Computer, Dec. 2007, pp. 33-37.
17. W.-C. Feng and K.W. Cameron, "The Green500 List: Encouraging Sustainable Supercomputing," Computer, Dec. 2007, pp. 50-55.
18. H. Sutter, "The Free Lunch Is Over—A Fundamental Turn Toward Concurrency in Software," Dr. Dobb's J., Mar. 2005; www.gotw.ca.
19. M. Creeger, "Multicore CPUs for the Masses," ACM Queue, Sept. 2005, pp. 64-ff.
20. J. Dongarra et al., "The Impact of Multicore on Computational Science Software," CTWatch Quarterly, Feb. 2007, pp. 3-10.
21. J. Larus and C. Kozyrakis, "Transactional Memory," Comm. ACM, July 2008, pp. 80-88.
22. L.S. Blackford et al., "An Updated Set of Basic Linear Algebra Subprograms (BLAS)," ACM Trans. Mathematical Software, vol. 28, no. 2, 2002, pp. 135-151.
23. A.C. Sodan, "Message Passing vs. Shared-Data Programming—Wish vs. Reality," Proc. 19th Int'l Symp. High-Performance Computing Systems (HPCS 05), IEEE CS Press, 2005, pp. 131-139.
24. A. Snavely and D.M. Tullsen, "Symbiotic Jobscheduling for a Simultaneous Multithreading Processor," Proc. 5th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 00), ACM Press, 2000, pp. 234-244.
25. J. Nakajima and V. Pallipadi, "Enhancements for Hyper-Threading Technology in the Operating System—Seeking the Optimal Scheduling," Proc. Usenix 2nd Workshop on Industrial Experiences with Systems Software, Usenix, Dec. 2002, pp. 25-38.
26. A.C. Sodan and L. Lan, "LOMARC—Lookahead Matchmaking for Multi-Resource Coscheduling on Hyperthreaded CPUs," IEEE Trans. Parallel and Distributed Computing, Nov. 2006, pp. 1360-1375.
27. A.C. Sodan et al., Benefits of Semi Time Sharing and Trading Time vs. Space in Computational Grids, tech. report 08-020, Univ. of Windsor, Dept. of Computer Science, May 2008.
28. R. Sasanka et al., "The Energy Efficiency of CMP vs. SMT for Multimedia Workloads," Proc. 18th Ann. Int'l Conf. Supercomputing (ICS 04), ACM Press, 2004, pp. 196-206.
16 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool