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| Josep Torrellas, "Architectures for Extreme-Scale Computing," Computer, vol. 42, no. 11, pp. 28-35, November, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/MC.2009.341, author = {Josep Torrellas}, title = {Architectures for Extreme-Scale Computing}, journal ={Computer}, volume = {42}, number = {11}, issn = {0018-9162}, year = {2009}, pages = {28-35}, doi = {http://doi.ieeecomputersociety.org/10.1109/MC.2009.341}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - Computer TI - Architectures for Extreme-Scale Computing IS - 11 SN - 0018-9162 SP28 EP35 EPD - 28-35 A1 - Josep Torrellas, PY - 2009 KW - Computer architecture KW - High-end computing KW - Energy and power efficiency KW - Programmability KW - Extreme-scale computing VL - 42 JA - Computer ER - | |||
1. P. Kogge et al., ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems, DARPA Information Processing Techniques Office (IPTO) sponsored study, 2008; www.cse.nd.edu/Reports/2008TR-2008-13.pdf .
2. E. Grochowski, and M. Annavaram, "Energy per Instruction Trends in Intel Microprocessors," Technology@Intel Magazine, Mar. 2006, pp. 1-8.
3. R. Dreslinski et al., "Near Threshold Computing: Overcoming Performance Degradation from Aggressive Voltage Scaling," Proc. Workshop Energy-Efficient Design, 2009, pp. 44-49.
4. B. Lee et al., "Architecting Phase Change Memory as a Scalable DRAM Alternative," Proc. Int'l Symp. Computer Architecture (ISCA 09), ACM Press, 2009, pp. 2-13.
5. R. Ramaswami and K. Sivarajan, Optical Networks: A Practical Perspective, Morgan Kaufmann, 2nd ed., 2002.
6. D. Vantrease et al., "Corona: System Implications of Emerging Nanophotonic Technology," Proc. Int'l Symp. Computer Architecture (ISCA 08), IEEE Press, 2008, pp. 153-164.
7. J. Shirako et al., "Phasers: a Unified Deadlock-Free Construct for Collective and Point-to-Point Synchronization," Proc. Int'l Conf. Supercomputing (SC 08), ACM Press, 2008, pp. 277-288.
8. M. Prvulovic, Z. Zhang, and J. Torrellas, "ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors," Proc. Int'l Symp. Computer Architecture (ISCA 02), ACM Press, 2002, pp. 111-122.
9. J. Brodman et al., "New Abstractions for Data Parallel Programming," Proc. First Usenix Workshop on Hot Topics in Parallelism (HotPar), Usenix Assoc., 2009; www.usenix.org/event/hotpar09/tech/full_papers/ brodmanbrodman.pdf.
10. J. Tuck et al., "SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization," Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 08), ACM Press, 2008, pp. 145-156.

