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| John Lach, Vinu Vijay Kumar, "Application-Specific Product Generics," Computer, vol. 42, no. 8, pp. 64-74, August, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/MC.2009.244, author = {John Lach and Vinu Vijay Kumar}, title = {Application-Specific Product Generics}, journal ={Computer}, volume = {42}, number = {8}, issn = {0018-9162}, year = {2009}, pages = {64-74}, doi = {http://doi.ieeecomputersociety.org/10.1109/MC.2009.244}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - Computer TI - Application-Specific Product Generics IS - 8 SN - 0018-9162 SP64 EP74 EPD - 64-74 A1 - John Lach, A1 - Vinu Vijay Kumar, PY - 2009 KW - Nonrecurring engineering costs KW - FPGAs KW - ASICs KW - High-level synthesis VL - 42 JA - Computer ER - | |||
1. K-C. Wu, and Y-W. Tsai, "Structured ASIC: Evolution or Revolution?" Proc. 2004 Int'l Symp. Physical Design (ISPD 04), ACM Press, 2004, pp. 103-106.
2. K. Kim, R. Karri, and M. Potkonjak, "Synthesis of Application Specific Programmable Processors," Proc. 34th Ann. Conf. Design Automation (DAC 97), ACM Press, 1997, pp. 353-358.
3. B. Troxel et al., "A Hybrid ASIC and FPGA Architecture," Proc. 2002 IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 02), ACM Press, 2002, pp. 187-194.
4. K. Compton and S. Hauck, "Flexibility Measurement of Domain-Specific Reconfigurable Hardware," Proc. 2004 ACM/SIGDA 12th Int'l Symp. Field-Programmable Gate Arrays (FPGA 04), ACM Press, 2004, pp. 155-161.
5. V. Vijay Kumar and J. Lach, "Designing, Scheduling, and Allocating Flexible Arithmetic Components," Field-Programmable Logic and Applications, LNCS 2778, Springer, 2003, pp. 1166-1169.
6. K. Dale et al., "Applications of Small-Scale Reconfigurability to Graphics Processors," Reconfigurable Computing: Architectures and Applications, LNCS 3985, Springer, 2006, pp. 99-108.
7. V. Vijay Kumar and J. Lach, "Heterogeneous Redundancy for Fault and Defect Tolerance with Complexity Independent Area Overhead," Proc. 18th IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems (DFT 03), IEEE CS Press, 2003, pp. 571-578.
8. S.M.S.A. Chiricescu et al., "Morphable Multipliers," Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, LNCS 2438, Springer, 2002, pp. 647-656.
9. V. Vijay Kumar and J. Lach, "Highly Flexible Multi-Mode System Synthesis," Proc. 3rd IEEE/ACM/IFIP Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES + ISS 05), ACM Press, 2005, pp. 27-32.
10. P.G. Paulin and J.P. Knight, "Force-Directed Scheduling for the Behavioral Synthesis of ASICs," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, June 1989, pp. 661-679.
11. R.M. Haralick and L.G. Shapiro, Computer and Robot Vision, Addison-Wesley, 1992.
12. D.J. Mallon and P.B. Denyer, "A New Approach to Pipeline Optimisation," Proc. Conf. European Design Automation (EURO-DAC 90), IEEE CS Press, 1990, pp. 83-88.
13. K. Högstedt and A. Orailoglu, "Integrating Binding Constraints in the Synthesis of Area-Efficient Self-Recovering Microarchitectures," Proc. 1994 IEEE Int'l Conf. Computer Design (ICCD 94), IEEE CS Press, 1994, pp. 331-334.
14. R. Karri and A. Orailoglu, "High-Level Synthesis of Fault-Secure Microarchitectures," Proc. 30th Ann. Design Automation Conf. (DAC 93), ACM Press, 1993, pp. 429-433.
15. S. Park and K. Choi, "Performance-Driven High-Level Synthesis with Bit-Level Chaining and Clock Selection," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Feb. 2001, pp. 199-212.

