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Issue No.07 - July (2008 vol.41)
pp: 40-46
Greg Stitt , University of Florida
Frank Vahid , University of California, Riverside
ABSTRACT
Warp processing dynamically and transparently transforms an executing microprocessor's binary kernels into customized field-programmable gate array (FPGA) circuits, commonly resulting in 2X to 100X speedup over executing on microprocessors. A new architecture and set of dynamic CAD tools demonstrate warp processing's potential.
INDEX TERMS
FPGA, warp processing, embedded systems, just-in-time compilation, dynamic synthesis, reconfigurable computing
CITATION
Greg Stitt, Frank Vahid, "Warp Processing: Dynamic Translation of Binaries to FPGA Circuits", Computer, vol.41, no. 7, pp. 40-46, July 2008, doi:10.1109/MC.2008.240
REFERENCES
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10. G. Stitt et al., "Hardware/Software Partitioning of Software Binaries: A Case Study of H.264 Decode," Proc. Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES/ISSS 05), ACM Press, 2005, pp. 285–290.
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12. G. Stitt and F. Vahid, "Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators," Proc. Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES/ISSS 07), ACM Press, 2007, pp. 93–98.
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