The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.07 - July (2008 vol.41)
pp: 27-32
William J. Dally , Stanford University
James Balfour , Stanford University
David Black-Shaffer , Stanford University
James Chen , Stanford University
R. Curtis Harting , Stanford University
Vishal Parikh , Stanford University
Jongsoo Park , Stanford University
David Sheffield , Stanford University
ABSTRACT
Hardwired ASICs—50X more efficient than programmable processors—sacrifice programmability to meet the efficiency requirements of demanding embedded systems. Programmable processors use energy mostly to supply instructions and data to the arithmetic units, and several techniques can reduce instruction- and data-supply energy costs. Using these techniques in the Stanford ELM processor closes the gap with ASICs to within 3X.
INDEX TERMS
embedded computing, ASICs, low-power programmable processors
CITATION
William J. Dally, James Balfour, David Black-Shaffer, James Chen, R. Curtis Harting, Vishal Parikh, Jongsoo Park, David Sheffield, "Efficient Embedded Computing", Computer, vol.41, no. 7, pp. 27-32, July 2008, doi:10.1109/MC.2008.224
REFERENCES
1. O. Silven and K. Jyrkkä, "Observations on Power-Efficiency Trends in Mobile Communication Devices," EURASIP J. Embedded Systems, vol. 2007, no. 1, 2007, p. 17.
2. S. Hsu et al., "A 2GHz 13.6mW 12x9b Multiplier for Energy Efficient FFT Accelerators," Proc. 31st European Solid-State Circuits Conf., IEEE Press, 2005, pp. 199–202.
3. T.R. Halfhill, "MIPS Threads the Needle," Microprocessor Report, Feb. 2006, vol. 20, part 2, pp. 1–8.
4. E. Grochowski and M. Annavaram, "Energy per Instruction Trends in Intel Microprocessors," Technology@Intel Magazine, Mar. 2006, pp. 1–8.
6 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool