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| Ralph Cavin, James A. Hutchby, Victor Zhirnov, Joe E. Brewer, George Bourianoff, "Emerging Research Architectures," Computer, vol. 41, no. 5, pp. 33-37, May, 2008. | |||
| BibTex | x | ||
| @article{ 10.1109/MC.2008.155, author = {Ralph Cavin and James A. Hutchby and Victor Zhirnov and Joe E. Brewer and George Bourianoff}, title = {Emerging Research Architectures}, journal ={Computer}, volume = {41}, number = {5}, issn = {0018-9162}, year = {2008}, pages = {33-37}, doi = {http://doi.ieeecomputersociety.org/10.1109/MC.2008.155}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - Computer TI - Emerging Research Architectures IS - 5 SN - 0018-9162 SP33 EP37 EPD - 33-37 A1 - Ralph Cavin, A1 - James A. Hutchby, A1 - Victor Zhirnov, A1 - Joe E. Brewer, A1 - George Bourianoff, PY - 2008 KW - morphic architectures KW - multicore chips KW - CMOS platforms KW - hybrid computation VL - 41 JA - Computer ER - | |||
1. V. Sriram et. al., "An 80-Tile, 1.28 TFLOPS Network-on-Chip in 65 nm CMOS," Proc. Int'l Solid-State Circuits Conf. (ISSCC 07), Session 5.2, Microprocessors, IEEE Press, 2007, pp. 5–7.
2. "Perspectives on Nano-Architectures," SRC working paper, 2006.
3. K. Asanovic et al., The Landscape of Parallel Computing Research: A View from Berkeley, tech. report UCB/EECS-2006-183, Dept. Electrical Eng. and Computer Science, Univ. of Calif., Berkeley, 2006.
4. V.V. Zhirnov et al., "Emerging Research Logic Devices," IEEE Circuits &Devices, vol. 21, no. 3, 2003, pp. 37–46.
5. J.A. Hutchby et al., "Emerging Research Memory and Logic Technologies—A Critical Review of the Technologies Based on New Relevance/Evaluation Criteria," IEEE Circuits &Devices, vol. 21, no. 3, 2003, pp. 47–51.
6. K.K. Likharev and D.B. Strukov, CMOL: Devices, Circuits, and Architectures, Introduction to Molecular Electronics, Springer, 2005, pp. 447–477.
7. G. Snider and S. Williams, "Nano/CMOS Architectures Using Field-Programmable Interconnect," Nanotechnology, vol. 18, 2007, pp. 1–11.
8. R. Sarpeshkar, "Going beyond Moore's Law with Analog and Bio-Inspired Processing," Proc. Emerging Research Devices Workshop (Architectures), 2006.
9. V. Beiu, "A Novel, Highly Reliable, Low Power, Nano Architecture When Von Neumann Augments Komolgorov," Proc. 15th Int'l Conf. Application-Specific Systems, Architectures, and Processors, IEEE Press, 2004, pp. 167–178.
10. R. Sarpeshkar, "Brain Power: Borrowing From Biology for Low Power Computing," IEEE Spectrum, vol. 43, no. 5, 2006, pp. 24–29.
11. V. Beiu, "A Novel, Highly Reliable, Low Power, Nano Architecture: When Von Neumann Augments Komolgorov," Proc. 15th Int'l Conf. Application-Specific Systems, Architectures, and Processors, IEEE Press, 2004, pp. 167–178.
12. R. Sarpeshkar and M. O'Halloran, "Scalable Hybrid Computation with Spikes," Neural Computation, ACM, vol. 14, no. 9, 2002, pp. 2003–2024.
13. Marcus Kaiser, "Brain Architecture: A Design for Natural Computation, Philosophical. Trans. Royal Soc. A, vol. 365, 2007, pp. 3033–3045.
14. D. Hammerstrom, "Biologically Inspired Architectures," Information Technology, Wiley, 2006,
15. D. Kobayashi, T. Shibata, and Y. Fujimori, "A Ferroelectric Associative Memory Employing Heterogate FGMOS Structure, IEEE Trans. Electron Devices, vol. 52, 2005, pp. 2188–2197.
16. P. Foldesy et al., "Digital Implementation of Cellular Sensor-Computers," Int'l J. Circuit Theory and Applications, vol. 34, no. 4, 2006, pp. 409–428.
17. T. Roska, "Computational and Computer Complexity of Analogic Cellular Wave Computers," J. Circuits, Systems, and Computers, vol. 12, 2003, pp. 539–562.