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Issue No.02 - February (2008 vol.41)
pp: 69-76
Esam El-Araby , George Washington University
Miaoqing Huang , George Washington University
Kris Gaj , George Mason University
Volodymyr Kindratenko , University of Illinois at Urbana-Champaign
Tarek El-Ghazawi , George Washington University
ABSTRACT
Several high-performance computers now use field-programmable gate arrays as reconfigurable coprocessors. The authors describe the two major contemporary HPRC architectures and explore the pros and cons of each using representative applications from remote sensing, molecular dynamics, bioinformatics, and cryptanalysis.
INDEX TERMS
reconfigurable computing, high-performance computing, HPRC systems, field-programmable gate arrays
CITATION
Esam El-Araby, Miaoqing Huang, Kris Gaj, Volodymyr Kindratenko, Tarek El-Ghazawi, "The Promise of High-Performance Reconfigurable Computing", Computer, vol.41, no. 2, pp. 69-76, February 2008, doi:10.1109/MC.2008.65
REFERENCES
1. M. Taher and T. El-Ghazawi, "A Segmentation Model for Partial Run-Time Reconfiguration," Proc. IEEE Int'l Conf. Field Programmable Logic and Applications, IEEE Press, 2006, pp. 1–4.
2. T. El-Ghazawi, "Experience with Early Reconfigurable High-Performance Computers," 2006; http://hpcl.seas.gwu.edu/talksTarek_DATE2006.ppt .
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8. O.D. Fidanci et al., "Implementation Trade-Offs of Triple DES in the SRC-6E Reconfigurable Computing Environment," Proc. 5th Ann. Int'l Conf. Military and Aerospace Programmable Logic Devices, 2002; www.gwu.edu/~hpc/rcm/publicationsMAPLD2002.pdf .
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