SEPTEMBER 2006 (Vol. 39, No. 9) p. 94
0018-9162/06/$31.00 © 2006 IEEE
Published by the IEEE Computer Society
Published by the IEEE Computer Society
|LogicVision and Dolphin Announce Embedded Test and Repair Collaboration|
|Eve Offers ZeBu-UF4 Ultra-Fast Emulator Verification Platform|
|Mentor Graphics Launches nm-Scale Verification Solution|
|Synopsys Debuts Powerful PrimeYield Tool Suite|
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LogicVision and Dolphin Announce Embedded Test and Repair Collaboration
LogicVision, a provider of yield-learning capabilities that let its customers quickly and efficiently improve product yields, and Dolphin Technology, a provider of performance-optimized system-on-chip memory cores and performance-matched standard cell libraries, have announced an integrated, comprehensive, self-testable, and self-repairable memory solution for advanced nanometer designs. The integrated solution consists of Dolphin's high-performance 90- and 65-nanometer memories and LogicVision's recently announced ETMemory comprehensive automation suite. Dolphin's enhanced RAMpiler and RAMpiler+ memory compilers and LogicVision's LV2005 automation tools combine to provide a seamless, fully automated, embedded test and repair integration flow.
"A successful memory strategy requires not only the right memories, but the right test and repair capabilities as well," said Dolphin president Mo Tamjidi. "The combination of our memories with LogicVision's embedded test technology results in an excellent solution for the repair of embedded memory space, helping our customers reduce their time to market while maximizing yield."
For full product details, visit www.logicvision.com or www.dolphin-ic.com.
Eve Offers ZeBu-UF4 Ultra-Fast Emulator Verification Platform
Eve, a Silicon Valley-based provider of high-speed emulation and prototyping solutions, has added a new product to its growing ZeBu (zero-bug) family, a line of hardware-assisted verification platforms that support simultaneous hardware and embedded software verification.
ZeBu-UF4 (UF stands for ultrafast) shortens time to tapeout, improves product quality, eliminates costly respins, and accelerates software development. A new register-transfer-level front end extends the ZeBu compiler from a gate-level netlist to an RTL design description and includes field-programmable gate array synthesis capabilities.
The new ZeBu-UF4 platform includes four Xilinx Virtex-4 LX200 FPGAs that accommodate designs of up to six million application-specific integrated circuit logic gates, with four gigabits of memory capacity. Based on a mother/daughter-configured peripheral component interconnect card, it features an extensive low-voltage differential swing interconnect array implemented on a 68-layer printed circuit board.
ZeBu's front end maps an RTL design into an array of FPGAs, automatically handling all the required tasks, including parsing, synthesis, clustering, and clocktree, bus, and memory handling.
To learn more about Eve and the ZeBu line, visit www.eve-team.com.
Mentor Graphics Launches nm-Scale Verification Solution
Design rule checking has been the gold standard for the seamless handoff of integrated circuit designs to the manufacturer. Based on a pass/no-pass compliance method, the system was simple and straightforward, giving designers a faster method of sign-off and measurable assurance for successful silicon. But at the 130-nanometer node, DRC-clean designs began failing first silicon. Calibre nmDRC, from Oregon-based Mentor Graphics, overcomes the physical verification challenges of nanometer design. With its new "Hyperscaling" processing architecture, it also produces swift DRC run times and can scale to 100 CPUs.
Calibre nmDRC, based on the Calibre nm platform, provides model-based verification and analysis, and visualizations that guide the designer to key errors. Full integration with popular layout environments and direct-read capabilities lets designers invoke DRC and debug results seamlessly within their design flow.
Complete product details are available at www.mentor.com.
Synopsys Debuts Powerful PrimeYield Tool Suite
In a move that gives integrated circuit designers more control over the manufacturability of their designs, Synopsys recently launched its new PrimeYield tool suite. Built for 65-nanometer and smaller technology nodes, PrimeYield integrates design with manufacturing by accurately predicting design-induced mechanisms that threaten manufacturing tolerances and by providing automated correction guidance to upstream design implementation tools.
PrimeYield is built on production-baseline technology and manufacturing models used by leading foundries and integrated device manufacturers. The new suite drives automatic correction within Synopsys' IC Compiler advanced physical implementation solution, and accurate parasitic extraction within the Star-RCXT tool.
Synopsys' Raul Camposano says, "High accuracy and fast turnaround time are the cornerstones of predictable success. With its ability to help prevent critical problems before they become a production threat, PrimeYield gives designers more control over their designs' manufacturability."
To learn more about PrimeYield and other Synopsys products, see www.synopsys.com.