MARCH 2006 (Vol. 39, No. 3) pp. 75
0018-9162/06/$31.00 © 2006 IEEE

Published by the IEEE Computer Society
Protocollum by Bellum Creates Complex Protocol Models
Bellum Software announces the debut of its first commercial product, Protocollum, a visual tool for the design and protocol mapping of complex electronic system designs such as large ASICs and custom chips. The new tool offers engineers the ability to create a high-level architectural model that supports graphical visualization and user interaction.
Protocollum lets users capture and edit the rules that define protocol behavior. These rules become an executable model, which can then be run in a visual environment for design testing. Alternative methods today consist of interpreting English-language specifications provided in printed documentation.
Protocollum can create a protocol model in a fraction of the time required for interpreting plain-English specifications. Using a graphical layout similar to a message sequence chart, engineers can create relationships and connections for objects that come from well-defined classes such as Msg_, Event_, Rule_, and so on.
For more information about Bellum and Protocollum, visit
Nascentric Releases Speedy Nascim Fast-SPICE Simulator
Nascim, a next-generation simulation solution recently released by Nascentric, provides a 10X runtime improvement over other Fast-SPICE engines. Nascim's unique, nonlinear device models, combined with its current-based simulation approach, can help overcome some of the drawbacks of traditional Fast-SPICE tools.
Nascim's intelligent transformations and efficient processing of devices such as diodes, inductors, transistor, cells, and interconnects provide the performance needed to analyze large SoC designs under sharp time constraints. To ensure accurate simulation results, Nascim employs topology-aware circuit concepts to determine precise silicon behavior. SPICE-level accuracy is then achieved via careful modeling of transistors, complex devices, and hierarchical partitions in the design.
Nascim manages, stores, manipulates, and retrieves billions of transactions related to the simulation of transistors and complex interconnects, while current-based device models help reflect current flow in actual CMOS circuitry.
To download a complete Nascim data sheet, visit
M2000 Announces New FlexEOS eFPGA Core
Embedded field-programmable gate arrays from M2000 give real on-silicon hardware configurability to ASIC designs.
M2000's new FlexEOS eFPGA cores are IP macros designed to be included in ASIC, SoC, and ASSP circuits. This results in a hybrid chip that combines the features of an FPGA with those of an ASIC, SoC, or ASSP circuit. The embedded FPGA core is used to modify the chip's functionality after manufacture, even after the chip has been installed in a product.
FlexEOS cores offer other advantages to chip designers, including high performance, deterministic timing, high scalability, and high silicon densities.
Visit for complete product details.
Giga Scale Integration Launches InCyte Estimation Tool
InCyte, a new chip estimation tool from Giga Scale Integration, dramatically reduces the risk, design time, and cost of integrated circuit design. It accurately estimates key IC specifications, including size, power, leakage, yield, and cost, all during the architectural design stage. InCyte lets users explore and quantify designs across various technology nodes, process variants, IP libraries, and packages
Giga Scale makes a no-cost version of InCyte available to any user who registers at This version, also known as InCyte Lite, performs chip estimations based on industry-average foundry and IP library data. Once downloaded, InCyte Lite can be upgraded to InCyte Enterprise, which is dedicated to performing accurate estimations of specific third-party IP libraries and foundry process nodes.
For answers to frequently asked questions or to download a product information sheet, visit

Protocollum, a visual tool for protocol mapping, lets users capture and edit the rules that define protocol behavior.