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Scaling to the End of Silicon with EDGE Architectures
July 2004 (vol. 37 no. 7)
pp. 44-55
Doug Burger, The University of Texas at Austin
Stephen W. Keckler, The University of Texas at Austin
Kathryn S. McKinley, The University of Texas at Austin
Mike Dahlin, The University of Texas at Austin
Lizy K. John, The University of Texas at Austin
Calvin Lin, The University of Texas at Austin
Charles R. Moore, The University of Texas at Austin
James Burrill, The University of Texas at Austin
Robert G. McDonald, The University of Texas at Austin
William Yoder, The University of Texas at Austin
the TRIPS Team, The University of Texas at Austin
Post-RISC microprocessor designs must introduce new ISAs to address the challenges that modern CMOS technologies pose while also exploiting the massive levels of integration now possible. To meet these challenges, the TRIPS Team at the University of Texas at Austin has developed a new class of ISAs, called Explicit Data Graph Execution, that will match the characteristics of semiconductor technology over the next decade.

EDGE architectures appear to offer a progressively better solution as technology scales down to the end of silicon, with each generation providing a richer spatial substrate at the expense of increased global communication delays.

Citation:
Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Mike Dahlin, Lizy K. John, Calvin Lin, Charles R. Moore, James Burrill, Robert G. McDonald, William Yoder, the TRIPS Team, "Scaling to the End of Silicon with EDGE Architectures," Computer, vol. 37, no. 7, pp. 44-55, July 2004, doi:10.1109/MC.2004.65
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