Scaling to the End of Silicon with EDGE Architectures

Doug Burger; Mike Dahlin; Lizy K. John; Stephen W. Keckler; Kathryn S. McKinley; the TRIPS Team; William Yoder; Robert G. McDonald; Calvin Lin; James Burrill; Charles R. Moore

doi:10.1109/MC.2004.65

Computer
2004
Issue No. 7 - July
Abstract - Scaling to the End of Silicon with EDGE Architectures

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	Similar Articles Articles by Doug Burger Articles by Stephen W. Keckler Articles by Kathryn S. McKinley Articles by Mike Dahlin Articles by Lizy K. John Articles by Calvin Lin Articles by Charles R. Moore Articles by James Burrill Articles by Robert G. McDonald Articles by William Yoder Articles by the TRIPS Team

Scaling to the End of Silicon with EDGE Architectures

July 2004 (vol. 37 no. 7)

pp. 44-55

	ASCII Text	x
	Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Mike Dahlin, Lizy K. John, Calvin Lin, Charles R. Moore, James Burrill, Robert G. McDonald, William Yoder, the TRIPS Team, "Scaling to the End of Silicon with EDGE Architectures," Computer, vol. 37, no. 7, pp. 44-55, July, 2004.

	BibTex	x
	@article{ 10.1109/MC.2004.65, author = {Doug Burger and Stephen W. Keckler and Kathryn S. McKinley and Mike Dahlin and Lizy K. John and Calvin Lin and Charles R. Moore and James Burrill and Robert G. McDonald and William Yoder and the TRIPS Team}, title = {Scaling to the End of Silicon with EDGE Architectures}, journal ={Computer}, volume = {37}, number = {7}, issn = {0018-9162}, year = {2004}, pages = {44-55}, doi = {http://doi.ieeecomputersociety.org/10.1109/MC.2004.65}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - Computer TI - Scaling to the End of Silicon with EDGE Architectures IS - 7 SN - 0018-9162 SP44 EP55 EPD - 44-55 A1 - Doug Burger, A1 - Stephen W. Keckler, A1 - Kathryn S. McKinley, A1 - Mike Dahlin, A1 - Lizy K. John, A1 - Calvin Lin, A1 - Charles R. Moore, A1 - James Burrill, A1 - Robert G. McDonald, A1 - William Yoder, A1 - the TRIPS Team, PY - 2004 VL - 37 JA - Computer ER -

Doug Burger, The University of Texas at Austin

Stephen W. Keckler, The University of Texas at Austin

Kathryn S. McKinley, The University of Texas at Austin

Mike Dahlin, The University of Texas at Austin

Lizy K. John, The University of Texas at Austin

Calvin Lin, The University of Texas at Austin

Charles R. Moore, The University of Texas at Austin

James Burrill, The University of Texas at Austin

Robert G. McDonald, The University of Texas at Austin

William Yoder, The University of Texas at Austin

the TRIPS Team, The University of Texas at Austin

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MC.2004.65

Post-RISC microprocessor designs must introduce new ISAs to address the challenges that modern CMOS technologies pose while also exploiting the massive levels of integration now possible. To meet these challenges, the TRIPS Team at the University of Texas at Austin has developed a new class of ISAs, called Explicit Data Graph Execution, that will match the characteristics of semiconductor technology over the next decade.

EDGE architectures appear to offer a progressively better solution as technology scales down to the end of silicon, with each generation providing a richer spatial substrate at the expense of increased global communication delays.

Citation:

Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Mike Dahlin, Lizy K. John, Calvin Lin, Charles R. Moore, James Burrill, Robert G. McDonald, William Yoder, the TRIPS Team, "Scaling to the End of Silicon with EDGE Architectures," Computer, vol. 37, no. 7, pp. 44-55, July 2004, doi:10.1109/MC.2004.65

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