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Reliable and Efficient System-on-Chip Design
March 2004 (vol. 37 no. 3)
pp. 42-50
Naresh R. Shanbhag, University of Illinois at Urbana-Champaign

To increase processor performance, the microprocessor industry is scaling feature sizes into the deep submicron and sub-100-nanometer regime. The recent emergence of noise and the dramatic increase in process variations have raised serious questions about using nanometer process technologies to design reliable, low-power, high-performance computing systems.

The design and electronic design automation communities must work closely with the process engineering community to address these problems. Specifically, researchers must explore the tradeoffs between reliability and energy efficiency at the device, circuit, architectural, algorithmic, and system levels.

Citation:
Naresh R. Shanbhag, "Reliable and Efficient System-on-Chip Design," Computer, vol. 37, no. 3, pp. 42-50, March 2004, doi:10.1109/MC.2004.1274003
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