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Programming Models for Hybrid CPU/FPGA Chips
January 2004 (vol. 37 no. 1)
pp. 118-120
David Andrews, University of Kansas
Douglas Niehaus, University of Kansas
Peter Ashenden, Ashenden Designs

Components that combine a CPU and reconfigurable logic gates need a programming model that abstracts the computational hardware.

Citation:
David Andrews, Douglas Niehaus, Peter Ashenden, "Programming Models for Hybrid CPU/FPGA Chips," Computer, vol. 37, no. 1, pp. 118-120, Jan. 2004, doi:10.1109/MC.2004.1260732
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