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A Formal Approach to MpSoC Performance Verification
April 2003 (vol. 36 no. 4)
pp. 60-67
Kai Richter, Technical University of Braunschweig
Marek Jersak, Technical University of Braunschweig
Rolf Ernst, Technical University of Braunschweig

Multiprocessor system on chip designs use complex on-chip networks to integrate different programmable processor cores, specialized memories, and other components on a single chip.

MpSoCs have become the architecture of choice in many industries. Their heterogeneity inevitably increases with intellectual-property integration and component specialization. System integration is becoming a major challenge in their design.

Simulation is state of the art in MpSoC performance verification, but it has conceptual disadvantages that become disabling as complexity increases. Formal approaches offer a systematic alternative.

Citation:
Kai Richter, Marek Jersak, Rolf Ernst, "A Formal Approach to MpSoC Performance Verification," Computer, vol. 36, no. 4, pp. 60-67, April 2003, doi:10.1109/MC.2003.1193230
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