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A Formal Approach to MpSoC Performance Verification
April 2003 (vol. 36 no. 4)
pp. 60-67
| ASCII Text | x | ||
| Kai Richter, Marek Jersak, Rolf Ernst, "A Formal Approach to MpSoC Performance Verification," Computer, vol. 36, no. 4, pp. 60-67, April, 2003. | |||
| BibTex | x | ||
| @article{ 10.1109/MC.2003.1193230, author = {Kai Richter and Marek Jersak and Rolf Ernst}, title = {A Formal Approach to MpSoC Performance Verification}, journal ={Computer}, volume = {36}, number = {4}, issn = {0018-9162}, year = {2003}, pages = {60-67}, doi = {http://doi.ieeecomputersociety.org/10.1109/MC.2003.1193230}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - Computer TI - A Formal Approach to MpSoC Performance Verification IS - 4 SN - 0018-9162 SP60 EP67 EPD - 60-67 A1 - Kai Richter, A1 - Marek Jersak, A1 - Rolf Ernst, PY - 2003 VL - 36 JA - Computer ER - | |||
Multiprocessor system on chip designs use complex on-chip networks to integrate different programmable processor cores, specialized memories, and other components on a single chip.
MpSoCs have become the architecture of choice in many industries. Their heterogeneity inevitably increases with intellectual-property integration and component specialization. System integration is becoming a major challenge in their design.
Simulation is state of the art in MpSoC performance verification, but it has conceptual disadvantages that become disabling as complexity increases. Formal approaches offer a systematic alternative.
Citation:
Kai Richter, Marek Jersak, Rolf Ernst, "A Formal Approach to MpSoC Performance Verification," Computer, vol. 36, no. 4, pp. 60-67, April 2003, doi:10.1109/MC.2003.1193230
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