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Queuing Simulation Model for Multiprocessor Systems
February 2003 (vol. 36 no. 2)
pp. 58-64
Thin-Fong Tsuei, Sun Microsystems
Wayne Yamamoto, Sun Microsystems

The processor queuing model provides memory-hierarchy and system-design evaluation of memory-intensive commercial online-transaction-processing workloads on large multi-processor systems. It differs from detailed cycle-accurate and direct-execution simulations in that it does not simulate instruction execution. Instead, as in analytical models, the authors build processor and workload characteristics that are easy to collect and estimate.

Because the authors believe that the processor model's function is to accurately generate memory traffic to the rest of the system, they model a minimal set of processor and workload characteristics that captures the important interactions between a complex processor and the system-memory hierarchy.

Thin-Fong Tsuei, Wayne Yamamoto, "Queuing Simulation Model for Multiprocessor Systems," Computer, vol. 36, no. 2, pp. 58-64, Feb. 2003, doi:10.1109/MC.2003.1178049
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