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Issue No.12 - December (2002 vol.35)
pp: 29-34
Chris Rowen , Tensilica
ABSTRACT
<p>To remain competitive, system-on-chip designers must keep pace with silicon technology's rapid evolution. One approach to speeding development of megagate SoCs uses multiple micro-processor cores to perform much of the processing currently relegated to register-transfer-level (RTL) techniques. Although general-purpose embedded processors handle many tasks, they often lack the bandwidth needed to perform particularly complex jobs, such as audio and video processing. Hence the historic rise of RTL use in SoC design.</p><p>Developers can configure a new class of processor--extensible microprocessor cores--to bring the required amount and type of processing bandwidth to bear on many embedded tasks. Because these processors employ firmware instead of RTL-defined hardware for their control algorithm, designers can develop and verify processor-based task engines for many embedded SoC tasks more quickly and easily.</p>
CITATION
Chris Rowen, "Reducing SoC Simulation and Development Time", Computer, vol.35, no. 12, pp. 29-34, December 2002, doi:10.1109/MC.2002.1106176
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