This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Reducing SoC Simulation and Development Time
December 2002 (vol. 35 no. 12)
pp. 29-34
Chris Rowen, Tensilica

To remain competitive, system-on-chip designers must keep pace with silicon technology's rapid evolution. One approach to speeding development of megagate SoCs uses multiple micro-processor cores to perform much of the processing currently relegated to register-transfer-level (RTL) techniques. Although general-purpose embedded processors handle many tasks, they often lack the bandwidth needed to perform particularly complex jobs, such as audio and video processing. Hence the historic rise of RTL use in SoC design.

Developers can configure a new class of processor--extensible microprocessor cores--to bring the required amount and type of processing bandwidth to bear on many embedded tasks. Because these processors employ firmware instead of RTL-defined hardware for their control algorithm, designers can develop and verify processor-based task engines for many embedded SoC tasks more quickly and easily.

Citation:
Chris Rowen, "Reducing SoC Simulation and Development Time," Computer, vol. 35, no. 12, pp. 29-34, Dec. 2002, doi:10.1109/MC.2002.1106176
Usage of this product signifies your acceptance of the Terms of Use.