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EPIC: Explicitly Parallel Instruction Computing
February 2000 (vol. 33 no. 2)
pp. 37-45

Over the past two and a half decades, the computer industry has grown accustomed to the spectacular rate of increase in microprocessor performance. The industry accomplished this without fundamentally rewriting programs in parallel form, without changing algorithms or languages, and often without even recompiling programs. Instruction-level parallel processing achieves high performance without major changes to software.

However, computers have thus far achieved this goal at the expense of tremendous hardware complexity--a complexity that has grown so large as to challenge the industry's ability to deliver ever-higher performance. The authors developed the Explicitly Parallel Instruction Computing (EPIC) style of architecture to enable higher levels of instruction-level parallelism without unacceptable hardware complexity. They focus on the broader concept of EPIC as embodied by HPL-PD (formerly known as HPL PlayDoh) architecture, which encompasses a large space of possible EPIC ISAs (instruction set architectures). In this article, the authors focus on HPL-PD because it represents the essence of the EPIC philosophy while avoiding the idiosyncracies of a specific ISA.

Citation:
Michael S. Schlansker, B. Ramakrishna Rau, "EPIC: Explicitly Parallel Instruction Computing," Computer, vol. 33, no. 2, pp. 37-45, Feb. 2000, doi:10.1109/2.820037
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