Issue No.05 - May (1998 vol.31)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/2.675637
The microprocessor industry can capably predict the clock frequency and functionality of first silicon?the first small set of chips made for a new design. However, predicting first silicon?s performance on real programs remains a challenge. Microprocessor designers use performance models to evaluate how new ideas affect performance. However, it is very difficult to know if these models are accurate. The problem lies in understanding the true performance effect of a new feature. In an unstable performance model, model changes may inadvertently remove existing bugs, introduce new bugs, or reduce the performance impact of an existing bug. This effect can mislead designers into implementing features that do not actually improve performance or not implementing features that would. This article presents experimental results on calibrating a performance model against actual hardware, and on the basis of these results, suggests a systematic method for validating performance models. These results highlight the difficulty in developing an accurate performance model. As microarchitecture complexity continues to increase, especially with the incorporation of aggressive speculation techniques, accurate performance modeling and the validation of performance models will continue to be a great challenge.
Bryan Black, John Paul Shen, "Calibration of Microprocessor Performance Models", Computer, vol.31, no. 5, pp. 59-65, May 1998, doi:10.1109/2.675637