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Asynchronous Processor Survey
November 1997 (vol. 30 no. 11)
pp. 67-76

Virtually all computers today are synchronous, thanks to an internal timing device that regulates processing. As systems grow increasingly large and complex, however, this little device-the clock-can cause big problems with clock skew, a timing delay that can create havoc with the overall design. It can also increase the circuit silicon and power dissipation.

In seeking to overcome such limitations, computer architecture researchers are actively considering asynchronous processor design. Asynchronous architectures permit modular design: Each subsystem or functional block can be optimized without being synchronized to a global clock. Moreover, an asynchronous system exhibits the average performance of all components, rather than the worst-case performance of a single component. Asynchronous processors may also reduce power dissipation by inherently shutting down unused portions of the circuit.

This article examines the key architecture issues that concern designers and compares six developmental asynchronous architectures. Though asynchronous processors may not match the performance of synchronous processors now, the condition generating the research into asynchronous processors will grow more prevalent as device geometries continue to shrink.

Tony Werner, Venkatesh Akella, "Asynchronous Processor Survey," Computer, vol. 30, no. 11, pp. 67-76, Nov. 1997, doi:10.1109/2.634866
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