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Trace Processors: Moving to Fourth-Generation Microarchitectures
September 1997 (vol. 30 no. 9)
pp. 68-74
| ASCII Text | x | ||
| James E. Smith, Sriram Vajapeyam, "Trace Processors: Moving to Fourth-Generation Microarchitectures," Computer, vol. 30, no. 9, pp. 68-74, September, 1997. | |||
| BibTex | x | ||
| @article{ 10.1109/2.612251, author = {James E. Smith and Sriram Vajapeyam}, title = {Trace Processors: Moving to Fourth-Generation Microarchitectures}, journal ={Computer}, volume = {30}, number = {9}, issn = {0018-9162}, year = {1997}, pages = {68-74}, doi = {http://doi.ieeecomputersociety.org/10.1109/2.612251}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - Computer TI - Trace Processors: Moving to Fourth-Generation Microarchitectures IS - 9 SN - 0018-9162 SP68 EP74 EPD - 68-74 A1 - James E. Smith, A1 - Sriram Vajapeyam, PY - 1997 VL - 30 JA - Computer ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/2.612251
T his article proposes a new architecture called "trace processors," which consist of multiple, distributed on-chip processor cores, each of which simultaneously executes a different trace. All but one core executes the traces speculatively, having used branch prediction to select traces that follow the one executing. (Although this architectural concept is similar to multiscalar processors, described in a sidebar, it does not require explicit compiler support). The authors argue that future processors will rely heavily on replication and hierarchy, and they show how their architecture exploits these concepts.
Citation:
James E. Smith, Sriram Vajapeyam, "Trace Processors: Moving to Fourth-Generation Microarchitectures," Computer, vol. 30, no. 9, pp. 68-74, Sept. 1997, doi:10.1109/2.612251
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