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Will Physical Scalability Sabotage Performance Gains?
September 1997 (vol. 30 no. 9)
pp. 37-39

The most important physical trend facing chip architects is the fact that on-chip wires are becoming much slower relative to logic as the on-chip devices shrink. The author points out that it will soon be impossible to maintain one global clock over the entire chip, and sending signals across a billion-transistor processor may require as many as 20 cycles.

Citation:
Doug Matzke, "Will Physical Scalability Sabotage Performance Gains?," Computer, vol. 30, no. 9, pp. 37-39, Sept. 1997, doi:10.1109/2.612245
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