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Branch Effect Reduction Techniques
May 1997 (vol. 30 no. 5)
pp. 71-81

The insatiable demand of both old and new applications demand improved capabilities. Developers must exploit parallelism for all types of programs to realize gains. Multiprocessor, multithreaded, vector, and dataflow computers achieve speedups up to the 1,000's for programs with large amounts of data parallelism or independent control flow.

General-purpose code, however, has many conditional branches, irregular control flow, and much less data parallelism. These code characteristics and their detrimental consequences, in the form of branch effects, have severely limited the parallelism that can be exploited. Branch effects result from the uncertainties in the way branches execute.

This article surveys techniques to reduce branch effects and describes their relative merits, including examples from commercial machines. Branch effect reduction techniques can be implemented in hardware, software, or both to free up more parallelism and speed up the execution of general-purpose code.

Research is bearing fruit: Speedups of 10 or more are being demonstrated in research simulations and may be realized in hardware within a few years.

Citation:
Augustus K. Uht, Vijay Sindagi, Sajee Somanathan, "Branch Effect Reduction Techniques," Computer, vol. 30, no. 5, pp. 71-81, May 1997, doi:10.1109/2.589913
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