This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
VMW: A Visualization-Based Microarchitecture Workbench
December 1995 (vol. 28 no. 12)
pp. 57-64
Single-chip microprocessors are achieving phenomenal performance due to advances being made in several enabling technologies. But this performance increase is accompanied by increasing processor complexity. The design of complex superscalar processors requires using sophisticated software tools, most notably simulators. Most existing simulators, however, suffer from three weaknesses. They lack retargetability, visualization support, and interactive control. This article describes the Visualization-Based Microarchitecture Workbench (VMW), which addresses these weaknesses. VMW enables a processor architect to efficiently and effectively explore the machine design space. A designer can use VMW to rigorously specify a new microarchitecture, automatically generate a performance simulator for the machine, and quickly assess machine performance. Performance data are machine-cycle accurate and can be viewed using a rich set of visualization instruments provided by VMW. Simulators for the DEC Alpha AXP 21064 and 21164, the IBM RS/6000, and the PowerPC 601and 620 microprocessors (and modifications and extensions of these machines) have been generated and executed. VMW has been demonstrated at a number of industrial sites, and its public domain distribution is planned.
Citation:
Trung A. Diep, John Paul Shen, "VMW: A Visualization-Based Microarchitecture Workbench," Computer, vol. 28, no. 12, pp. 57-64, Dec. 1995, doi:10.1109/2.476200
Usage of this product signifies your acceptance of the Terms of Use.