Recent advances in the design and synthesis of integrated circuits have prompted system architects to investigate computer aided design methods for systems that contain both application-specific and predesigned reprogrammable components. For the most part, we can apply high level synthesis techniques to synthesis of systems containing processors by treating the latter as a generalized resource. However, the problem is more complex, since the software on the processor implements system functionality in an instruction-driven manner with a statically allocated memory space, whereas ASICs operate as data driven reactive elements. Due to these differences in computational models and primitive operations in hardware and software, a new formulation of the problem of cosynthesis is needed. The authors present their cosynthesis approach. They specify system behavior using HardwareC, a hardware description language (HDL) that has a C-like syntax and supports timing and resource constraints. It also supports specification of unbounded and unknown delay operations that can arise from data-dependent decisions and external synchronization operations. The particular choice of a HDL to specify system functionality is immaterial for the cosynthesis formulation here, and other HDLs such as Verilog could be used.