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Processor and Memory-Based Checkpoint and Rollback Recovery
February 1993 (vol. 26 no. 2)
pp. 22-31

Several hardware-based techniques that support checkpoint and rollback recovery are presented. The focus is on hardware schemes for uniprocessors, shared-memory multiprocessors, and distributed virtual-memory systems. A taxonomy for processor and memory techniques based on the memory hierarchy is presented. This provides a basis for understanding subtle differences among the various schemes. Processor-based schemes that handle transient faults by using processor-based transparent rollback techniques and memory-based schemes that roll back data instead of instructions and can be integrated with the processor techniques or can be exploited by higher levels of software are discussed.

Citation:
Nicholas S. Bowen, Dhiraj K. Pradhan, "Processor and Memory-Based Checkpoint and Rollback Recovery," Computer, vol. 26, no. 2, pp. 22-31, Feb. 1993, doi:10.1109/2.191981
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