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| David L. Landis, Nitin Nigam, Joseph W. Yoder, Vijay K. Jain, Hiroomi Hikawa, D.C. Keezer, "Wafer-Scale Optimization Using Computational Availability," Computer, vol. 25, no. 4, pp. 66-75, April, 1992. | |||
| BibTex | x | ||
| @article{ 10.1109/2.129051, author = {David L. Landis and Nitin Nigam and Joseph W. Yoder and Vijay K. Jain and Hiroomi Hikawa and D.C. Keezer}, title = {Wafer-Scale Optimization Using Computational Availability}, journal ={Computer}, volume = {25}, number = {4}, issn = {0018-9162}, year = {1992}, pages = {66-75}, doi = {http://doi.ieeecomputersociety.org/10.1109/2.129051}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - Computer TI - Wafer-Scale Optimization Using Computational Availability IS - 4 SN - 0018-9162 SP66 EP75 EPD - 66-75 A1 - David L. Landis, A1 - Nitin Nigam, A1 - Joseph W. Yoder, A1 - Vijay K. Jain, A1 - Hiroomi Hikawa, A1 - D.C. Keezer, PY - 1992 VL - 25 JA - Computer ER - | |||
It is shown that, given the ability to restructure wafer-level designs, there are different ways to employ redundancy. Redundancy is evaluated by estimating system computational availability over a mission lifetime. This technique is illustrated using two wafer-scale integration (WSI) case studies. The first is a very-fine-grained programmable systolic data processor (PSDP) that contains 4- and 8-b paths, RAM, and control optimized for signal and data processing applications. The second, the Mosaic multicomputer architecture, is a less fine-grained homogeneous architecture in which each node contains a 16-b microprocessor and associated RAM and ROM. Potential benefits of implementing these parallel processing architectures in wafer scale are discussed.