This Article 
 Bibliographic References 
 Add to: 
Wafer-Scale Optimization Using Computational Availability
April 1992 (vol. 25 no. 4)
pp. 66-75

It is shown that, given the ability to restructure wafer-level designs, there are different ways to employ redundancy. Redundancy is evaluated by estimating system computational availability over a mission lifetime. This technique is illustrated using two wafer-scale integration (WSI) case studies. The first is a very-fine-grained programmable systolic data processor (PSDP) that contains 4- and 8-b paths, RAM, and control optimized for signal and data processing applications. The second, the Mosaic multicomputer architecture, is a less fine-grained homogeneous architecture in which each node contains a 16-b microprocessor and associated RAM and ROM. Potential benefits of implementing these parallel processing architectures in wafer scale are discussed.

David L. Landis, Nitin Nigam, Joseph W. Yoder, Vijay K. Jain, Hiroomi Hikawa, D.C. Keezer, "Wafer-Scale Optimization Using Computational Availability," Computer, vol. 25, no. 4, pp. 66-75, April 1992, doi:10.1109/2.129051
Usage of this product signifies your acceptance of the Terms of Use.