This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Configuring a Wafer-Scale Two-Dimensional Array of Single-Bit Processors
April 1992 (vol. 25 no. 4)
pp. 29-39

An overview of the ELSA (European large SIMD array) project, which uses a two-level strategy to achieve defect tolerance for wafer-scale architectures implemented in silicon, is presented. The target architecture is a 2-D array of processing elements for low-level image processing. An array is divided into subarrays called chips. At the chip level, defect tolerance is proved by an extra column of PEs (processing element) and bypassing techniques. At the wafer level, a double-rail connection network is used to construct a target array of defect-free chips that is as large and as fast as possible. Its main advantage is being independent of chip defects, as it is controlled from the I/O pads. An algorithm for constructing an optimized two-dimensional array on a wafer containing a given number of defect-free PEs and connections, a method to program the switches for the target architecture found by the algorithm, and software for programming the switches using laser cuts are discussed.

Citation:
Ahmed Boubekeur, Jean-Luc Patry, Gabriele Saucier, Jacques Trilhe, "Configuring a Wafer-Scale Two-Dimensional Array of Single-Bit Processors," Computer, vol. 25, no. 4, pp. 29-39, April 1992, doi:10.1109/2.129043
Usage of this product signifies your acceptance of the Terms of Use.