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A Design and Yield Evaluation Technique for Wafer-Scale Memory
April 1992 (vol. 25 no. 4)
pp. 19-27
ASCII Text
x 
 
Koichi Yamashita, Shohei Ikehara, "A Design and Yield Evaluation Technique for Wafer-Scale Memory," Computer, vol. 25, no. 4, pp. 19-27, April, 1992.
 
 
BibTex
x
 
@article{ 10.1109/2.129042,
author = {Koichi Yamashita and Shohei Ikehara},
title = {A Design and Yield Evaluation Technique for Wafer-Scale Memory},
journal ={Computer},
volume = {25},
number = {4},
issn = {0018-9162},
year = {1992},
pages = {19-27},
doi = {http://doi.ieeecomputersociety.org/10.1109/2.129042},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - Computer
TI - A Design and Yield Evaluation Technique for Wafer-Scale Memory
IS - 4
SN - 0018-9162
SP19
EP27
EPD - 19-27
A1 - Koichi Yamashita,
A1 - Shohei Ikehara,
PY - 1992
VL - 25
JA - Computer
ER -
 

Wafer-scale memory provides greater yet cheaper storage volume than conventional memory systems using discrete chips. A simulator using a Monte Carlo technique to evaluate the defect tolerance scheme for a wafer-scale memory and predict the harvested capacity of the wafer memory is described. The design of a wafer-scale random-access memory that uses switching-register network logic is presented. A simulator that selects the optimal defect tolerance scheme for the wafer-scale memory is discussed.

Citation:
Koichi Yamashita, Shohei Ikehara, "A Design and Yield Evaluation Technique for Wafer-Scale Memory," Computer, vol. 25, no. 4, pp. 19-27, April 1992, doi:10.1109/2.129042
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