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Design Techniques for Testable Embedded Error Checkers
July 1990 (vol. 23 no. 7)
pp. 84-88
ASCII Text
x 
 
E.J. McCluskey, "Design Techniques for Testable Embedded Error Checkers," Computer, vol. 23, no. 7, pp. 84-88, July, 1990.
 
 
BibTex
x
 
@article{ 10.1109/2.56855,
author = {E.J. McCluskey},
title = {Design Techniques for Testable Embedded Error Checkers},
journal ={Computer},
volume = {23},
number = {7},
issn = {0018-9162},
year = {1990},
pages = {84-88},
doi = {http://doi.ieeecomputersociety.org/10.1109/2.56855},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - Computer
TI - Design Techniques for Testable Embedded Error Checkers
IS - 7
SN - 0018-9162
SP84
EP88
EPD - 84-88
A1 - E.J. McCluskey,
PY - 1990
VL - 23
JA - Computer
ER -
 

Design techniques to ensure the testability of embedded checkers that cannot be tested by scan-path bistables are presented. The discussion covers: types of error detectors; parity checkers and self-testing circuits; two-rail checkers; M-out-of-N checkers; and equality checkers. The techniques outline guarantee single stuck fault testability.

Citation:
E.J. McCluskey, "Design Techniques for Testable Embedded Error Checkers," Computer, vol. 23, no. 7, pp. 84-88, July 1990, doi:10.1109/2.56855
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