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Fault Tolerance in VLSI Circuits
July 1990 (vol. 23 no. 7)
pp. 73-83
ASCII Text
x 
 
Israel Koren, Adit D. Singh, "Fault Tolerance in VLSI Circuits," Computer, vol. 23, no. 7, pp. 73-83, July, 1990.
 
 
BibTex
x
 
@article{ 10.1109/2.56854,
author = {Israel Koren and Adit D. Singh},
title = {Fault Tolerance in VLSI Circuits},
journal ={Computer},
volume = {23},
number = {7},
issn = {0018-9162},
year = {1990},
pages = {73-83},
doi = {http://doi.ieeecomputersociety.org/10.1109/2.56854},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - Computer
TI - Fault Tolerance in VLSI Circuits
IS - 7
SN - 0018-9162
SP73
EP83
EPD - 73-83
A1 - Israel Koren,
A1 - Adit D. Singh,
PY - 1990
VL - 23
JA - Computer
ER -
 

The defects that can occur when manufacturing VLSI ICs and the faults that can result are described. Some commonly used restructuring techniques for avoiding defective components are discussed. Several defect-tolerant designs of memory ICs, logic ICs, and wafer-scale circuits are presented. Yield models for predicting the yield of chips with redundancy are introduced, and the optimal amount of redundancy is determined.

Citation:
Israel Koren, Adit D. Singh, "Fault Tolerance in VLSI Circuits," Computer, vol. 23, no. 7, pp. 73-83, July 1990, doi:10.1109/2.56854
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