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Issue No.06 - June (1990 vol.23)
pp: 71-83
ABSTRACT
<p>Directory-based and bus-based cache coherence schemes are defined and described. Directory-based schemes can be classified as centralized or distributed. Both categories support local caches to improve processor performance and reduce traffic in the interconnection. Schemes using presence flags, B pointers, and linked lists are discussed. Bus-based systems provide uniform memory access to all processors. This memory organization allows a simpler programming model, making it easier to develop new parallel applications or to move existing applications from a uniprocessor to a parallel system. Two architectural variations of bus-based systems are described: multiple-bus and hierarchical architectures.</p>
CITATION
Shreekant Thakkar, Michel Dubois, Anthony T. Laundrie, Gurindar S. Sohi, David V. James, Stein Gjessing, Manu Thapar, Bruce Delagi, Michael Carlton, Alvin Despain, "Scalable Shared-Memory Multiprocessor Architectures", Computer, vol.23, no. 6, pp. 71-83, June 1990, doi:10.1109/2.55502
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