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Compiler-Directed Cache Management in Multiprocessors
June 1990 (vol. 23 no. 6)
pp. 39-47

The necessity of finding alternatives to hardware-based cache coherence strategies for large-scale multiprocessor systems is discussed. Three different software-based strategies sharing the same goals and general approach are presented. They consist of a simple invalidation approach, a fast selective invalidation scheme, and a version control scheme. The strategies are suitable for shared-memory multiprocessor systems with interconnection networks and a large number of processors. Results of trace driven simulations conducted on numerical benchmark routines to compare the performance of the three schemes are presented.

Citation:
Hoichi Cheong, Alexander V. Veidenbaum, "Compiler-Directed Cache Management in Multiprocessors," Computer, vol. 23, no. 6, pp. 39-47, June 1990, doi:10.1109/2.55499
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