This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays
January 1990 (vol. 23 no. 1)
pp. 55-69

Focuses on the characterization and classification of reconfiguration techniques. The techniques are differentiated according to the type of redundancy (time or hardware), allocation of redundancy (local or global), replacement unit, (processor or a set of processors), switching domain (global or local), and switching implementation (switching element, bus, or network). Typical techniques from four major classes-set switching, processor switching, local redundancy, and time redundancy-are reviewed. The proposed taxonomy can be used as a guide for future research in design and analysis of reconfiguration schemes.

Citation:
Mengly Chean, Jose A.B. Fortes, "A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays," Computer, vol. 23, no. 1, pp. 55-69, Jan. 1990, doi:10.1109/2.48799
Usage of this product signifies your acceptance of the Terms of Use.