The authors examine the performance, cost, and schedule tradeoffs made for the NS 32532, a 32-bit general-purpose microprocessor. Among its features are a 30-MHz clock frequency, three on-chip caches, a four-stage pipeline, and dedicated mechanisms for multiprocessing support. The authors describe the design constraints set by the VLSI processing and packaging technologies. They address the issue of market requirements by examining the software and hardware considerations for the microprocessor's target applications. After describing the functional partitioning choices, including the means for supporting a memory hierarchy and floating-point operations, they present the NS32532's microarchitecture. They then examine the microprocessor's system interface, the memory reference transactions, and the instruction-flow and data-flow monitoring mechanisms. Finally, the authors present an overview of the methodology adopted to accomplish the design within a strict schedule while achieving full functionality and meeting cost and performance goals.