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Multiple-Valued Logic and Optimization of Programmable Logic Arrays
April 1988 (vol. 21 no. 4)
pp. 71-80
ASCII Text
x 
 
Tustomu Sasao, "Multiple-Valued Logic and Optimization of Programmable Logic Arrays," Computer, vol. 21, no. 4, pp. 71-80, April, 1988.
 
 
BibTex
x
 
@article{ 10.1109/2.52,
author = {Tustomu Sasao},
title = {Multiple-Valued Logic and Optimization of Programmable Logic Arrays},
journal ={Computer},
volume = {21},
number = {4},
issn = {0018-9162},
year = {1988},
pages = {71-80},
doi = {http://doi.ieeecomputersociety.org/10.1109/2.52},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - Computer
TI - Multiple-Valued Logic and Optimization of Programmable Logic Arrays
IS - 4
SN - 0018-9162
SP71
EP80
EPD - 71-80
A1 - Tustomu Sasao,
PY - 1988
VL - 21
JA - Computer
ER -
 

Shows a method of designing programmable logic arrays (PLAs) using multiple-valued input, two-valued output functions (MVITVOFs). A MVITVOF is an extension of the two-valued logic function. An expression for a MVITVOF directly represents a multiple-output PLA with decoders. Each product of the expression corresponds to each column of the PLA, so the number of products; in the expression equals the number of columns of the PLA. The array size of the PLA is proportional to the number of products; the PLA can thus be minimized by minimizing the expression.

Citation:
Tustomu Sasao, "Multiple-Valued Logic and Optimization of Programmable Logic Arrays," Computer, vol. 21, no. 4, pp. 71-80, April 1988, doi:10.1109/2.52
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