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VLSI implementation of a neural network model
March 1988 (vol. 21 no. 3)
pp. 41,42,43,44,45,46,47,48,49
The authors describe a complementary metal-oxide-semiconductor (CMOS) very-large-scale integrated (VLSI) circuit implementing a connectionist neural-network model. It consists of an array of 54 simple processors fully interconnected with a programmable connection matrix. This experimental design tests the behavior of a large network of processors integrated on a chip. The circuit can be operated in several different configurations by programming the interconnections between the processors. Tests made with the circuit working as an associative memory and as a pattern classifier were so encouraging that the chip has been interfaced to a minicomputer and is being used as a coprocessor in pattern-recognition experiments. This mode of operation is making it possible to test the chip's behavior in a real application and study how pattern-recognition algorithms can be mapped in such a network.<>
Index Terms:
VLSI,CMOS integrated circuits,computerised pattern recognition,neural nets,pattern-recognition,parallel processing,neural network model,complementary metal-oxide-semiconductor,CMOS,VLSI,programmable connection matrix,associative memory,pattern classifier,coprocessor,Very large scale integration,Neural networks,Computer networks,Integrated circuit interconnections,Circuit testing,Optical computing,Optical interconnections,Optical network units,Optical fiber networks,Biological system modeling
Citation:
"VLSI implementation of a neural network model," Computer, vol. 21, no. 3, pp. 41,42,43,44,45,46,47,48,49, March 1988, doi:10.1109/2.30
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