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December 1981 (vol. 14 no. 12)
pp. 103-111
| ASCII Text | x | ||
| M. Satyanarayanan, D. Bhandarkar, "Design Trade-Offs in VAX-11 Translation Buffer Organization," Computer, vol. 14, no. 12, pp. 103-111, December, 1981. | |||
| BibTex | x | ||
| @article{ 10.1109/C-M.1981.220301, author = {M. Satyanarayanan and D. Bhandarkar}, title = {Design Trade-Offs in VAX-11 Translation Buffer Organization}, journal ={Computer}, volume = {14}, number = {12}, issn = {0018-9162}, year = {1981}, pages = {103-111}, doi = {http://doi.ieeecomputersociety.org/10.1109/C-M.1981.220301}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - Computer TI - Design Trade-Offs in VAX-11 Translation Buffer Organization IS - 12 SN - 0018-9162 SP103 EP111 EPD - 103-111 A1 - M. Satyanarayanan, A1 - D. Bhandarkar, PY - 1981 KW - null VL - 14 JA - Computer ER - | |||
A major feature of the VAX-11 is its large virtual address space. This trace-driven simulation scheme evaluates address translation hardware that supports this feature cost-effectively.
Citation:
M. Satyanarayanan, D. Bhandarkar, "Design Trade-Offs in VAX-11 Translation Buffer Organization," Computer, vol. 14, no. 12, pp. 103-111, Dec. 1981, doi:10.1109/C-M.1981.220301
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