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Concurrent simulation of nearly identical digital networks
April 1974 (vol. 7 no. 4)
pp. 39-44
E. G. Ulrich, GTE Laboratories Inc.
T. Baker, GTE Laboratories Inc.
Test patterns for testing digital circuits are usually checked on a test verification program to determine if all or most of the possible faults will be detected. Historically, such a test verification program would be accomplished with many simulations: one for each possible fault.
Citation:
E. G. Ulrich, T. Baker, "Concurrent simulation of nearly identical digital networks," Computer, vol. 7, no. 4, pp. 39-44, April 1974, doi:10.1109/MC.1974.6323496
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