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Power Reduction Techniques for LSI Memory
January/February 1972 (vol. 5 no. 1)
pp. 31-39
F.S. Greene, TECHNOLOGY LEARNING CORP.
Power reduction techniques are described for both LSI memory components and systems. These techniques have been verified experimentally for both read-only and random access read/write components using power switching circuits external to the chips. A number of ways to apply on-chip power switching are described. The power switching concept is also described for memory cards and systems that can be organized into blocks.
Citation:
F.S. Greene, "Power Reduction Techniques for LSI Memory," Computer, vol. 5, no. 1, pp. 31-39, Jan.-Feb. 1972, doi:10.1109/C-M.1972.216865
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