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Issue No.04 - July/August (1999 vol.19)
pp: 14-17
CITATION
Y. Arthur Lin, "Parametric Wafer Map Visualization", IEEE Computer Graphics and Applications, vol.19, no. 4, pp. 14-17, July/August 1999, doi:10.1109/38.773959
REFERENCES
1. F. Lee, "Advanced Yield Enhancement: Integrated Yield Analysis," Proc. of IEEE/SEMI Advanced Semiconductor Manufacturing Conf.,Boston, MA, 1997, pp. 67-75.
2. J. Ousterhout, Tcl and the Tk Toolkit, Addison Wesley Longman, Reading, Mass., 1994.
3. S.S. Gleason, K.W. Tobin, and T.P. Karnowski, "Spatial Signature Analysis of Semiconductor Defects for Manufacturing Problem Diagnosis," Solid State Technology, July 1996, pp. 127-136, http:/www-ismv.ic.ornl.gov.
4. J.F. Bartlett, Don't Fidget with Widgets, Draw!, Digital Western Research Laboratory Tech. Report 91/6, Palo Alto, Calif., 1991, http://www.research.digital.com/wrl/projects/ Ezdhome.html.
5. J. Nijtmans, Dash Patch for Tk, http://home.wxs.nl/~nijtmansdash.html.
6. "Data Mining and Knowledge Discovery in Databases," Communications of the ACM, Vol. 39, No. 11, Nov. 1996, http://www.acm.org/cacm/nov96novtol.html .
7. L. Shon-Roy, A. Wiesnoski, and R. Zorich, Advanced Semiconductor Fabrication Handbook, Integrated Circuit Engineering Corp., Scottsdale, Ariz., 1998, http:/www.ice-corp.com.
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