The Truga001: A Scalable Rendering Processor

Tsuneo Ikedo; Jianhua Ma

doi:10.1109/38.656790

ComputerGraphics
1998
Issue No. 2 - March-April
Abstract - The Truga001: A Scalable Rendering Processor

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The Truga001: A Scalable Rendering Processor

March-April 1998 (vol. 18 no. 2)

pp. 59-79

	ASCII Text	x
	Tsuneo Ikedo, Jianhua Ma, "The Truga001: A Scalable Rendering Processor," IEEE Computer Graphics and Applications, vol. 18, no. 2, pp. 59-79, March-April, 1998.

	BibTex	x
	@article{ 10.1109/38.656790, author = {Tsuneo Ikedo and Jianhua Ma}, title = {The Truga001: A Scalable Rendering Processor}, journal ={IEEE Computer Graphics and Applications}, volume = {18}, number = {2}, issn = {0272-1716}, year = {1998}, pages = {59-79}, doi = {http://doi.ieeecomputersociety.org/10.1109/38.656790}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Computer Graphics and Applications TI - The Truga001: A Scalable Rendering Processor IS - 2 SN - 0272-1716 SP59 EP79 EPD - 59-79 A1 - Tsuneo Ikedo, A1 - Jianhua Ma, PY - 1998 VL - 18 JA - IEEE Computer Graphics and Applications ER -

Tsuneo Ikedo

Jianhua Ma

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/38.656790

The Truga001 is a single-chip rendering processor intended for virtual reality and multimedia systems. It has three main features: (1) multiple embedded functions with a MIMD structure that includes Phong shading, bump and texture mapping, reflection and refraction mapping, gaseous object rendering, shadow casting and hidden surface removal, (2) the combination of HDTV video camera images with CG images, and (3) scalability. It embeds twelve graphic processors and seven special modules in a single chip. The reconfigurable FIFO-memory pixel cache and three-dimensional frame buffer structure are used for high-speed transmission between the chip and frame buffers. A chip can simultaneously draw four million (10-pixel, arbitrarily sloped) vectors/s and render 1.2 million (1-pixel 3D triangles) polygons/s while applying Phong shading, bump and texture mapping, and hidden surface removal in a frame buffer system, implemented as a single-port DRAM. A system can also be scaled up with a parallel network of multiple Truga001s graphics processors. The chip can be fabricated in CMOS with 940.000 gates.

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Citation:

Tsuneo Ikedo, Jianhua Ma, "The Truga001: A Scalable Rendering Processor," IEEE Computer Graphics and Applications, vol. 18, no. 2, pp. 59-79, March-April 1998, doi:10.1109/38.656790

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