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Issue No.03 - May/June (1994 vol.14)
pp: 66-72
ABSTRACT
<p>This class of algorithms extends Bresenham's (1965) integer straight-line algorithm to generate more than one pixel per inner loop, thus reducing inner loop overhead. The quad-step algorithm is too large to justify its use in older hardware with limited memory space, but it can be viable in the context of modern memory and software sizes. Because the algorithm reduces both calculation overhead and the number of memory accesses for adjacent pixels, it can improve the performance of current systems that are limited in their processor speed and of future systems that might be limited in their memory speed. The algorithm gives results identical to those from Bresenham's single-step routine while drawing pixels in the expected direction from start to end point. Furthermore, as the gradual trend towards more bits per pixel continues, a processor supporting multi-word burst data instructions could make good use of this algorithm in speeding up line drawing into a 24-bits-per-pixel, 1-pixel-per-word color frame buffer. I chose to implement 4 steps per loop because it gave a useful performance improvement without exceeding the resources of the target processor, and it was small enough to hand-code. However, the techniques described can be used to construct a straight-line algorithm that generates more than 4 steps per loop. The relatively small average decision tree sizes indicate that algorithms of greater than 4 pixels per step might further improve line-drawing efficiency.</p>
CITATION
Graeme W. Gill, "N-Step Incremental Straight-Line Algorithms", IEEE Computer Graphics and Applications, vol.14, no. 3, pp. 66-72, May/June 1994, doi:10.1109/38.279047
REFERENCES
1. J.E. Bresenham, "Algorithm for Computer Control of a Digital Plotter,"IBM Systems J., Jan. 1965, pp. 25-30.
2. J. Boothroyd and P.A. Hamilton, "Exactly Reversible Plotter Paths,"Australian Computer J., Jan. 1965, pp. 25-30.
3. J. Bresenham, "Ambiguities in Incremental Line Rastering,"IEEE CG&A, Vol. 7, No. 5, May 1987, pp. 31-43.
4. J.E. Bresenham, "Run Length Slice Algorithm for Incremental Lines," inFundamental Algorithms for Computer Graphics, R.A. Earnshaw, ed., Springer-Verlag, New York, 1985.
5. G. Bao and J. G. Rokne, "Quadruple-Step Line Generation,"Computers&Graphics, Vol. 13, No. 4, 1989, pp. 461-469.
6. 80960KB Programmers Reference Manual, Intel Literature Sales, Santa Clara, Calif., 1988.
7. G.J. Myers, D.L. Budde, The 80960 Microprocessor Architecture, Wiley, New York, 1988.
8. J. G. Rokne, B. Wyvill, and X. Wu, "Fast Line Scan-Conversion,"ACM Trans. Graphics, Vol. 9, No. 4, Oct. 1990, pp. 376-388.
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