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Monolithic Architectures for Image Processing and Compression
November/December 1992 (vol. 12 no. 6)
pp. 75-86

Programmable IC architectures for image processing applications are reviewed. Chip sets that can be used for image and video compression and for traditional image processing systems like computer-vision systems, chip designs that can handle all three of the major multimedia compression, decompression, and transmission standards, ICs for generic image processing, and uniprocessor and multiprocessor image processing chips are discussed. Requirements for graphics architectures and image processing are outlined.

1. M.D. Edwards, "A Review of MIMD Architectures for Image Processing," J. Kittler and M.J.B. Duff, eds.,Image Processing system Architectures, Research Studies Press, Letchwork, Hertfordshire, England, 1985, pp. 85-101.
2. S. Yalamanchili et al., "Image Processing Architectures: A Taxonomy and Survey," inProgress in Pattern Recognition 2, L.N. Kanal and A. Rosenfeld, eds., Elsevier Science Publishers, North Holland, 1985, pp. 1-37.
3. T.J. Foundain, K.N. Matthews, and M.B. Duff, "The CLIP7A Image Processor,"IEEE Trans. Pattern Analysis and Machine Intelligence, Vol. 10, No 3, May 1988, pp. 310-319.
4. M. Kidode and Y. Shiraogawa, "High Speed Image Processor: TOSPIX-II," inEvaluation of Multicomputers, L.M. Uhr et al., Academic Press, New York, 1986, pp. 319-335.
5. N.L. Seed et al., "An Enhanced Transputer Module for Real-time Image Processing,"Third Int'l Conf. Image Processing and Its Applications, IEE, Hitchen, Herts, England, 1989, pp. 131-135.
6. K.S. Mills, G.K. Wong, and Y. Kim, "A High Performance Floating-Point Image Computing Workstation for Medical Applications,"Medical Imaging IV: Image Capture and Display, Vol. 1232, 1990, pp. 246-256.
7. JPEG-1 DIS, Draft International Standard, DIS 10918-1, CCIIT Rec. T.81, Working Group 10, ComitéConsultatif International de Télégraphique et Téléphonique, New York, Jan. 2, 1992.
8. MPEG-I CD, Committee Draft ISO/IEC 11172, Working Group 11, International Standards Organization, IPSJ, Tokyo, Dec. 6, 1991.
9. K. Guttag et al., "A Single-Chip Multiprocessor for Multimedia: The MVP,"IEEE CG&A, Vol. 12, No. 6, Nov. 1992, pp. 53-64.
10. D. Pryce, "Monolithic Circuits Expedite Desktop Video,"EDN,Vol. 36, No. 22, Oct. 24, 1991, pp. 67-76.
11. "AUP-1300E Video Encoder," AT&T Product Note, AT&T Microelectronics, April 1992.
12. I. Tamitani et al, "An Encoder/Decoder Chip Set for the MPEG Video Standard,"IEEE ICASSP-92, CS Press, Los Alamitos, Calif., 1992, pp. 661-664.
13. "Using the IIT Vision Processor in JPEG Applications," Product Note, Integrated Information Technologies, Santa Clara, Calif., Sept. 1991.
14. A. Razavi et al., "VLSI Implementation of an Image Compression Algorithm with a New Bit Rate Control Capability",IEEE ICASSP-92, Vol. 5, CS Press, Los Alamitos, Calif., 1992, pp. 669-672.
15. T. Araki et al., "The Architecture of a Vector Digital Signal Processor For Video Coding",IEEE ICASSP-92, Vol. 5, CS Press, Los Alamitos. Calif., 1992, pp. 681-684.
16. "Digital Signal Processing Data Book," tech. memo, LSI Logic Corp., Milpitas, Calif., Sept. 1991.
17. B. Pratt,Digital Image Processing, 2nd edition, John Wiley and Sons, New York, 1992.
18. K. Kikuchi et al., "A Single Chip 16-bit 25 Ns Real-time Video/image Signal Processor,"IEEE J. Solid State Circuits, Vol. 24, No. 6, Dec. 1989, pp. 1662-1667.
19. K. Kaneko et al., "A 50 ns DSP with Parallel Processing Architecture,"IEEE ISSCC 87, CS Press, Los Alamitos, Calif., 1987, pp. 158-159.
20. T. Murakami et al., "A DSP Architectural Design for Low Bit-rate Motion Video Codec,"IEEE Trans. Circuits and Systems, Vol. 36, No. 10, Oct. 1989, pp. 1,267-1,274.
21. A. Kanuma et al., "A 20 MHz 32b Pipelined CMOS Image Processor,"IEEE ISSCC 86, CS Press, Los Alamitos, Calif., 1986, pp. 102-103.
22. H. Yamada et al., "A Microprogrammable Real-Time Image Processor,"IEEE J. Solid State Circuitry, Vol. 23, No. 1, Jan. 1988, pp. 216- 223.
23. J.P. Norsworthy et al., "A Parallel Image Processing Chip,"IEEE ISSCC 88, 1988, CS Press, Los Alamitos, Calif., pp. 158-159.
24. D. Pfeiffer, "Integrating Image Processing with Standard Workstation Platforms,"Computer Technology Review, Summer 1991, pp. 103-107.
25. K. Aono, M. Toyokura, and T. Araki, "A 30 ns (600 MOPS) Image Processor with a Reconfigurable Pipeline Architecture,"IEEE 1989 Custom Integrated Circuits Conf., 1989, CS Press, Los Alamitos, Calif., pp. 24.4.1-24.4.4.
26. M. Maruyama et al., "An Image Signal Multiprocessor on a Single Chip,"IEEE J. Solid-State Circuits, Vol. 25, No. 6, Dec. 1990, pp. 1,476-1,483.
27. T. Minami et al., "A 300-MOPS Video Signal Processor with a Parallel Architecture,"IEEE J. Solid-State Circuits, Vol. 26, No. 12, Dec. 91, pp. 1,868-1,875.
28. R.J. Gove, "Architectures for Single-Chin Image Computing,"SPIE Electronic Imaging in Science and Technology Conf. on image Processing and Interchange, Vol. 1659, SPIE, San Jose, Calif., 1992, pp. 30-40.
29. H.K. Reghbati and A.C. Lee,Computer Graphics Hardware: Image Generation and Display, CS Press, Los Alamitos, Calif., 1988.

Konstantinos Konstantinides, Vasudev Bhaskaran, "Monolithic Architectures for Image Processing and Compression," IEEE Computer Graphics and Applications, vol. 12, no. 6, pp. 75-86, Nov.-Dec. 1992, doi:10.1109/38.163627
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