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Breaking the Frame-Buffer Bottleneck with Logic-Enhanced Memories
November/December 1992 (vol. 12 no. 6)
pp. 65-74

Logic-enhanced memory chips that can remove the rasterizer/frame buffer bottleneck which limits the performance of current image-generation architectures are discussed. Putting pixel memory on-chip with rasterizing processors provides the two to three orders of magnitude improvement in access rates needed to support realistic shading models and aliasing in interactive systems. Current high-performance graphics systems and logic-enhanced memory architectural issues are reviewed. The design of the PixelFlow Enhanced Memory Chip (EMC), which exploits advances in semiconductor technology and circuit techniques to build compact, high-performance rasterizers, is described.

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John Poulton, John Eyles, Steve Molnar, Henry Fuchs, "Breaking the Frame-Buffer Bottleneck with Logic-Enhanced Memories," IEEE Computer Graphics and Applications, vol. 12, no. 6, pp. 65-74, Nov.-Dec. 1992, doi:10.1109/38.163626
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