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| John Poulton, John Eyles, Steve Molnar, Henry Fuchs, "Breaking the Frame-Buffer Bottleneck with Logic-Enhanced Memories," IEEE Computer Graphics and Applications, vol. 12, no. 6, pp. 65-74, November/December, 1992. | |||
| BibTex | x | ||
| @article{ 10.1109/38.163626, author = {John Poulton and John Eyles and Steve Molnar and Henry Fuchs}, title = {Breaking the Frame-Buffer Bottleneck with Logic-Enhanced Memories}, journal ={IEEE Computer Graphics and Applications}, volume = {12}, number = {6}, issn = {0272-1716}, year = {1992}, pages = {65-74}, doi = {http://doi.ieeecomputersociety.org/10.1109/38.163626}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Computer Graphics and Applications TI - Breaking the Frame-Buffer Bottleneck with Logic-Enhanced Memories IS - 6 SN - 0272-1716 SP65 EP74 EPD - 65-74 A1 - John Poulton, A1 - John Eyles, A1 - Steve Molnar, A1 - Henry Fuchs, PY - 1992 VL - 12 JA - IEEE Computer Graphics and Applications ER - | |||
Logic-enhanced memory chips that can remove the rasterizer/frame buffer bottleneck which limits the performance of current image-generation architectures are discussed. Putting pixel memory on-chip with rasterizing processors provides the two to three orders of magnitude improvement in access rates needed to support realistic shading models and aliasing in interactive systems. Current high-performance graphics systems and logic-enhanced memory architectural issues are reviewed. The design of the PixelFlow Enhanced Memory Chip (EMC), which exploits advances in semiconductor technology and circuit techniques to build compact, high-performance rasterizers, is described.
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