|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
| ASCII Text | x | ||
| Roger D. Hersch, Pierre Demartines, Doris G. Fridman, Jean-Marc Aberle, Peter Pisan, Andre Decurnex, Ralf Rogner, "Multiprocessor Raster Plotting," IEEE Computer Graphics and Applications, vol. 12, no. 4, pp. 79-87, July/August, 1992. | |||
| BibTex | x | ||
| @article{ 10.1109/38.144830, author = {Roger D. Hersch and Pierre Demartines and Doris G. Fridman and Jean-Marc Aberle and Peter Pisan and Andre Decurnex and Ralf Rogner}, title = {Multiprocessor Raster Plotting}, journal ={IEEE Computer Graphics and Applications}, volume = {12}, number = {4}, issn = {0272-1716}, year = {1992}, pages = {79-87}, doi = {http://doi.ieeecomputersociety.org/10.1109/38.144830}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Computer Graphics and Applications TI - Multiprocessor Raster Plotting IS - 4 SN - 0272-1716 SP79 EP87 EPD - 79-87 A1 - Roger D. Hersch, A1 - Pierre Demartines, A1 - Doris G. Fridman, A1 - Jean-Marc Aberle, A1 - Peter Pisan, A1 - Andre Decurnex, A1 - Ralf Rogner, PY - 1992 VL - 12 JA - IEEE Computer Graphics and Applications ER - | |||
A scalable multiprocessor raster image processor that generates printed circuit plots in alternating band buffers is described. Synchronous raster plotting systems and the development of mask creation for producing printed circuits are reviewed. The general architecture of the multiprocessing system that rasterizes printed circuit plot descriptions, and its graphics, load prediction, and facet size computation operations are discussed. Performance analysis results of two versions of the multiprocessor architecture, one with four rasterization transputers and the other with eight, are presented.
1. L. Brunner, "Imagesetter Speed Comparison," Seybold Report on Publishing Systems, Vol. 20, No. 10, Feb. 1991.
2. I. Birk and J.M. McCrossin, "A Pipelined-Parallel Architecture for 2.5-D Batch Rasterizers,"Proc. Eurographics, North-Holland, Amsterdam, 1990, pp. 31-40.
3. M. Homewood et al., "The IMS T800 Transputer,"IEEE Micro, Vol. 7, No. 5, Oct. 1987, pp. 10-26.
4. R. Weiss, "32-bit Floating-Point DSP Processors,"EDN, Vol. 36, No. 23, Nov. 1991, pp. 127-146.
5. C. Peterson, J. Sutton, and P. Wiley, "iWarp: A 100-MOPS LIW Microprocessor for Multicomputers,"IEEE Micro, Vol. 11. No. 3, June 1951, pp. 26-29, 81-87.
6. A. Ben-Dor and B. Jones, "New Graphics Controller for Electrostatic Plotting."IEEE CG&A, Vol. 6, No. 1, Jan. 1986, pp. 16-25.
7. N. Andreiev, "Taking the Mystery out of Data Formats,"Printed Circuit Design, Vol. 6, No. 8, Aug. 1989, pp. 23-27.
8. R.D. Hersch, "Descriptive Contour Fill of Partly Degenerated Shapes."IEEE CG&A, Vol. 6, No. 7, July 1986, pp. 61-70.
9. R.D. Hersch, "Vertical Scan-conversion for Filling Purposes," inNew Trends in Computer Graphics, N. Magnenat-Thalmann and D. Thalmann. eds., Springer Verlag, New York, 1988, pp. 318-327.
10. R.D. Hersch, "Efficient Rendering of Outline Characters,"Proc. Society for Information Display, Vol. 32, No. 1, Jan. 1991, Palisades Institute for Research Services, New York, pp. 55-58.
11. U. decarlini and U. Villano,Transputeres and Parallel Architectures: Message-Passing Distributed Systems, Ellis Horwood, London, 1991.